Pipelined Diagonal Matrix Codes for Error Correction in Embedded Memories
Received: 11 May 2025 | Revised: 6 July 2025 and 14 July 2025 | Accepted: 19 July 2025 | Online: 6 October 2025
Corresponding author: C. H. Kavya
Abstract
Semiconductor memories are the basic storage elements for advanced FPGAs. However, with technology scaling due to high packing densities, the temperature of the device rises drastically, creating temporary or permanent faults that manifest as errors in the stored data. Permanent errors cannot be corrected, but temporary errors can. If the data in the memory is critical, such as data used during satellite or missile launch, patient data, etc., there is a need for Error-Detecting and Correcting (EDAC) code. Memories are represented as a matrix that stores data in rows. EDAC codes correct random (errors at various distributed locations) and burst errors (a sequence of erroneous bits within a row). The Hamming code represents the basis for any EDAC code. This work focuses on a single code used to identify 8-bit erroneous data and correct for 6 and 7 random bit errors and 8 burst errors. The matrix code utilizes a memory representation and Hamming code to detect and correct errors, taking care to increase the code rate with less area and delay. In addition, a pipelining technique is used to reduce power dissipation, which also helps to increase the speed of the design. The codes were modeled in Verilog HDL and verified for the Zynq 7000 series FPGA using Xilinx Vivado 2023.2. The results were verified for technological parameters, such as area in terms of LUTs, critical path delay, power dissipation, etc., and for non-technological parameters such as code rate, bit overhead, detection capability, correction capability, etc. The proposed pipelined matrix code was better in most aspects compared to existing designs.
Keywords:
bit overhead, code rate, errors, Hamming code, multiple cell upset, single error correction, syndrome bitsDownloads
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