High Clarity, Low Power: Achieving a 43× Speed Boost in Image Defogging Using FPGA Acceleration
Received: 5 May 2025 | Revised: 20 June 2025, 2 July 2025, and 5 July 2025 | Accepted: 8 July 2025 | Online: 6 October 2025
Corresponding author: Van Khoa Pham
Abstract
This study presents a Field-Programmable Gate Array (FPGA) accelerator designed for real-time image defogging at the edge, achieving high throughput and low power consumption. The design adapts the Dark Channel Prior (DCP) algorithm for hardware implementation using High-Level Synthesis (HLS) and incorporates advanced optimizations such as pipelining, loop unrolling, and dataflow control to enhance processing on resource-constrained devices. Implemented on a PYNQ-Z2 board running at just 100 MHz, the system achieves a remarkable 12.06 Frames per Second (FPS), surpassing a 2 GHz ARM processor by over 43× in speed. Power measurements show a low power consumption of 0.79 W, translating to a 153× improvement in energy efficiency (FPS/W) compared to an ARM-based software implementation. The proposed accelerator introduces a 4.7% pixel-level error, primarily affecting brightness consistency; nonetheless, it significantly outperforms processor-based approaches in both latency and power consumption. By demonstrating how FPGAs can sustain high-clarity image enhancement at the network edge, this work lays the groundwork for deployment in autonomous vehicles, remote surveillance systems, and environmental monitoring platforms where robust, low-power vision processing is critical.
Keywords:
Dark Channel Prior (DCP), High-Level Synthesis (HLS), hardware-accelerated system, real-time defogging, edge devicesDownloads
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