Design of an SLIM Cipher S-box with 8T-SRAM CiM for Energy-Efficient, Lightweight, and DPA Resistant Edge AI
Received: 2 May 2025 | Revised: 4 June 2025 and 18 June 2025 | Accepted: 21 June 2025 | Online: 16 July 2025
Corresponding author: Venkateswarlu Gonuguntla
Abstract
Side-channel attacks pose a significant threat to the security and trustworthiness of edge Artificial Intelligence (AI) devices, especially with the rise of AI-based hardware applications. In this work, a lightweight 8T-SRAM Computing-in-Memory (CiM) SLIM cipher S-box is proposed, with enhanced energy efficiency and resiliency to Differential Power Analysis (DPA) attacks. For the first time, the design utilizes Negative Capacitance Field-Effect Transistors (NCFETs). The reconfigurable nature of the proposed CiM architecture, in conjunction with the unique steep slope characteristics of NCFET-based logic gates, contributes to the enhancement of the overall S-box design's DPA resiliency and energy efficiency. The simulation results indicate that the proposed NCFET-based 8T-SRAM CiM S-box for the SLIM cipher exhibits ~3.8× lower energy consumption in comparison with the non-CiM S-box design at =0.5 V. The security evaluation of the proposed NCFET-based 8T-SRAM CiM S-box design for DPA attack demonstrates a 32× increase in the attacker effect ratio, a ~2.2× reduction in Signal-to-Noise Ratio (SNR), a ~43.4× improvement in the Security Power Delay (SPD), and a 32× increase in Measurements to Disclosure (MTD). These findings signify the enhanced security and trustworthiness of the 8T-SRAM CiM-based S-box design for SLIM cipher used in edge AI devices.
Keywords:
Computing-in-Memory (CiM), Differential Power Analysis (DPA), attack, hardware security, SRAM, ultra-lightweight block ciphers, trustworthy AI edge devicesDownloads
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Copyright (c) 2025 Koteswara Rao Penumalli, Tirumala Rao Kadiyam, Venu Birudu, Venkateswarlu Gonuguntla, Ramesh Vaddi
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