Design of an Array Multiplier for Computation in Memory Architecture
Received: 29 April 2025 | Revised: 2 July 2025, 14 July 2025, 23 July 2025, and 31 July 2025 | Accepted: 2 August 2025 | Online: 29 September 2025
Corresponding author: N. Shylashree
Abstract
The present computing landscape operates on the foundations of the von Neumann architecture, which, while influential, is accompanied by limitations in areas, such as the memory capacity, power consumption, and instruction parallelism. This configuration has direct implications for the effectiveness of modern computer systems. One of the new computation architectures to break these three boundaries is the Computation In Memory (CIM) architecture. This paper presents a CIM technique and arithmetic circuit co-design using an 8T SRAM cell, demonstrating arithmetic and Boolean logic operations in 45 nm CMOS technology. The use of Transmission Gate (TG)-based SRAM eliminates the need for peripheral circuitry during the read operations, reducing the delay and power consumption. The SRAM memory array must be created utilizing the 8T SRAM cell along with the proposed sensing scheme, a mapped 4-bit array multiplier net-list into a SRAM memory array, and was tested for functionality before the arithmetic circuit can be implemented. The read and write operations using the proposed TG-based architecture in the 2-bit array multiplier, reduces the processing delay by 80.63% and the power consumption by 93.53% when compared to the existing pass transistor logic-based design. The study presents a full-stack demonstration—from 8T SRAM cell design, sensing scheme, and memory array construction, to arithmetic circuit mapping and functional testing of the multiplier—showing a holistic view of the practical CIM implementation.
Keywords:
array multiplier, Computation In Memory (CIM), transmission-gate, SRAM, sense amplifier, memory modules, delay, MosFET circuits, digital integrated circuits, power dissipationDownloads
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