High-level Synthesis Integrated Verification

Authors

  • M. Dossis Department of Informatics Engineering, TEI of Western Macedonia, Kastoria, Greece
Volume: 5 | Issue: 5 | Pages: 864-870 | October 2015 | https://doi.org/10.48084/etasr.596

Abstract

It is widely known in the engineering community that more than 60% of the IC design project time is spent on verification. For the very complex contemporary chips, this may prove prohibitive for the IC to arrive at the correct time in the market and therefore, valuable sales share may be lost by the developing industry. This problem is deteriorated by the fact that most of conventional verification flows are highly repetitive and a great proportion of the project time is spent on last-moment simulations. In this paper we present an integrated approach to rapid, high-level verification, exploiting the advantages of a formal High-level Synthesis tool, developed by the author.  Verification in this work is supported at 3 levels: high-level program code, RTL simulation and rapid, generated C testbench execution. This paper is supported by strong experimental work with 3-4 popular design synthesis and verification that proves the principles of our methodology.

Keywords:

High-level Synthesis, Formal verification, E-DA

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How to Cite

[1]
M. Dossis, “High-level Synthesis Integrated Verification”, Eng. Technol. Appl. Sci. Res., vol. 5, no. 5, pp. 864–870, Oct. 2015.

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