Design and Comparative Analysis of High Speed and Low Power ALU Using RCA and Sklansky Adders for High-Performance Systems
Received: 9 February 2022 | Revised: 28 February 2022 | Accepted: 1 March 2022 | Online: 9 April 2022
Corresponding author: M. I. Khan
This study examines how different initial design decisions affect the area, timing, and power of technology-mapped designs. ASIC design flow, tools used during the flow, and the factors to consider to maximize the performance and power ratio are discussed. The ALU (Arithmetic Logic Unit) is a fundamental part of all processors. In this study, two ALUs were implemented using two different types of adder circuits: a Ripple Carry Adder (RCA) and a Sklansky adder. The Cadence EDA tools were used for the implementation. A comparative analysis was conducted for the two designed ALUs in terms of area, power, and timing analysis. The ALU design was also used as an example to examine the whole workflow front-end wise by constructing a block schematic and back-end wise by floorplanning, placing, and routing the physical design.
Keywords:arithmetic logic unit (ALU), ripple carry adder, sklansky adder, VHDL
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