AES High-Level SystemC Modeling using Aspect Oriented Programming Approach
Received: 29 November 2020 | Revised: 21 December 2020 | Accepted: 2 January 2021 | Online: 6 February 2021
The increasing complexity of the cryptographic modeling and security simulation of the Advanced Encryption Standard (AES) necessitate fast modeling and simulation security environment. The SystemC language is used in Electronic System Level (ESL) that allows cryptographic models to achieve high security and modeling simulation speed. Yet, the use of SystemC in the security simulation requires modifications of the original code which increases the modeling complexity. The Aspect-Oriented Programming (AOP) can be used in the cryptographic modeling and security simulations without any code modification. In this paper, a new AES SystemC model using the AOP technique is presented. A functional verification environment is proposed to test the functionality of the AES SystemC AOP model, the impact of AOP on simulation time, and the size of the executable files. The design of the AES model is developed with the weaving of all modules by AspectC++ which is an AOP language. The Simulation results show the efficiency of the proposed AES model and the uses of the AOP technique do not have a significant impact on simulation time or on the size of the executable file.
Keywords:security, cryptographic, AES, SystemC, AOP, high-level
H. Mestiri, N. Benhadjyoussef, and M. Machhout, "Fault Attacks Resistant AES Hardware Implementation," in 2019 IEEE International Conference on Design Test of Integrated Micro Nano-Systems (DTS), Gammarth-Tunis, Tunisia, Apr. 2019. https://doi.org/10.1109/DTSS.2019.8914979
J. Zhang, N. Wu, F. Zhou, F. Ge, and X. Zhang, "Securing the AES Cryptographic Circuit Against Both Power and Fault Attacks," Journal of Electrical Engineering & Technology, vol. 14, no. 5, pp. 2171-2180, Sep. 2019. https://doi.org/10.1007/s42835-019-00226-6
E. S. I. Harba, "Secure Data Encryption Through a Combination of AES, RSA and HMAC," Engineering, Technology & Applied Science Research, vol. 7, no. 4, pp. 1781-1785, Aug. 2017. https://doi.org/10.48084/etasr.1272
A. Alamer and B. Soh, "Design and Implementation of a Statistical Testing Framework for a Lightweight Stream Cipher," Engineering, Technology & Applied Science Research, vol. 10, no. 1, pp. 5132-5141, Feb. 2020. https://doi.org/10.48084/etasr.3250
B. Lin and F. Xie, "SCBench: A benchmark design suite for SystemC verification and validation," in 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), Jeju, South Korea, Jan. 2018, pp. 440-445. https://doi.org/10.1109/ASPDAC.2018.8297363
S. Aygün, L. Kouhalvandi, B. Örs, and E. O. Güneş, "Karatsuba Ofman Multiplication implementation on SystemC for Diffie-Hellman Key Exchange algorithm," in 2017 IEEE 4th International Conference on Knowledge-Based Engineering and Innovation (KBEI), Tehran, Iran, Dec. 2017, pp. 0641-0645. https://doi.org/10.1109/KBEI.2017.8324878
U. T. Gabor, C. von Egidy, and O. Spinczyk, "Interface Injection with AspectC++ in Embedded Systems," in 2019 IEEE 19th International Symposium on High Assurance Systems Engineering (HASE), Hangzhou, China, Jan. 2019, pp. 131-138. https://doi.org/10.1109/HASE.2019.00028
C. Borchert and O. Spinczyk, "Hardening an L4 Microkernel Against Soft Errors by Aspect-Oriented Programming and Whole-Program Analysis," ACM SIGOPS Operating Systems Review, vol. 49, no. 2, pp. 37-43, Jan. 2016. https://doi.org/10.1145/2883591.2883600
N. Veeranna and B. C. Schafer, "S3CBench: Synthesizable Security SystemC Benchmarks for High-Level Synthesis," Journal of Hardware and Systems Security, vol. 1, no. 2, pp. 103-113, Jun. 2017. https://doi.org/10.1007/s41635-017-0014-1
J. Treus and P. Herber, "Early Analysis of Security Threats by Modeling and Simulating Power Attacks in SystemC," in 2020 IEEE 91st Vehicular Technology Conference (VTC2020-Spring), Antwerp, Belgium, May 2020, pp. 1-5. https://doi.org/10.1109/VTC2020-Spring48590.2020.9129426
M. Bedoui, H. Mestiri, B. Bouallegue, and M. Machhout, "A reliable fault detection scheme for the AES hardware implementation," in 2016 International Symposium on Signal, Image, Video and Communications (ISIVC), Tunis, Tunisia, Nov. 2016, pp. 47-52. https://doi.org/10.1109/ISIVC.2016.7893960
M. Bedoui, H. Mestiri, B. Bouallegue, M. Marzougui, M. Qayyum, and M. Machhout, "An improved and efficient countermeasure against fault attacks for AES," in 2017 2nd International Conference on Anti-Cyber Crimes (ICACC), Abha, Saudi Arabia, Mar. 2017, pp. 209-212. https://doi.org/10.1109/Anti-Cybercrime.2017.7905292
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