Performance Optimization of 1-bit Full Adder Cell based on CNTFET Transistor

Authors

  • H. Ghabri National School of Engineering of Sfax, Tunisia
  • D. Ben Issa National School of Engineering of Sfax, Tunisia
  • H. Samet National School of Engineering of Sfax, Tunisia
Volume: 9 | Issue: 6 | Pages: 4933-4936 | December 2019 | https://doi.org/10.48084/etasr.3156

Abstract

The full adder is a key component for many digital circuits like microprocessors or digital signal processors. Its main utilization is to perform logical and arithmetic operations. This has empowered the designers to continuously optimize this circuit and ameliorate its characteristics like robustness, compactness, efficiency, and scalability. Carbon Nanotube Field Effect Transistor (CNFET) stands out as a substitute for CMOS technology for designing circuits in the present-day technology. The objective of this paper is to present an optimized 1-bit full adder design based on CNTFET transistors inspired by new CMOS full adder design [1] with enhanced performance parameters. For a power supply of 0.9V, the count of transistors is decreased to 10 and the power is almost split in two compared to the best existing CNTFET based adder. This design offers significant improvement when compared to existing designs such as C-CMOS, TFA, TGA, HPSC, 18T-FA adder, etc. Comparative data analysis shows that there is 37%, 50%, and 49% amelioration in terms of area, delay, and power delay product respectively compared to both CNTFET and CMOS based adders in existing designs. The circuit was designed in 32nm technology and simulated with HSPICE tools.

Keywords:

1-bit full adder, CNTFET, PDP, low power, HSPICE

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How to Cite

[1]
H. Ghabri, D. Ben Issa, and H. Samet, “Performance Optimization of 1-bit Full Adder Cell based on CNTFET Transistor”, Eng. Technol. Appl. Sci. Res., vol. 9, no. 6, pp. 4933–4936, Dec. 2019.

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