Thoughts on the Possibility of Damage of High-Voltage Electrical Insulation below the So-Called Inception Voltage: Simulation under a Superposition of AC and DC Voltage – Part III

Authors

  • M. Danikas Department of Electrical & Computer Engineering, Democritus University of Thrace, Greece
Volume: 8 | Issue: 4 | Pages: 3088-3092 | August 2018 | https://doi.org/10.48084/etasr.2017

Abstract

In a previous work, a typical case is studied, where a solid sheet insulation contains a void under DC or AC voltage. In the present paper, to study the charging phenomenon in HVDC valve windings and cables, a more complex case is studied under a superposition of AC and DC voltage. Real inception voltage is calculated, and it agrees with the experimental results reported in another paper. Moreover, the location of the charging phenomenon is calculated, and it is related to the ratio between AC and DC voltage.

Keywords:

partial discharges, charging phenomena below inception voltage, cavities, simulation

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References

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How to Cite

[1]
M. Danikas, “Thoughts on the Possibility of Damage of High-Voltage Electrical Insulation below the So-Called Inception Voltage: Simulation under a Superposition of AC and DC Voltage – Part III”, Eng. Technol. Appl. Sci. Res., vol. 8, no. 4, pp. 3088–3092, Aug. 2018.

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