MATLAB-Based Validation and Comparative Analysis of Quantum-Dot Transistor Compute-in-Memory Architecture for Neural Network Applications
Corresponding author: Abdulrahman Husawi
Abstract
This work provides independent validation and extended analysis of a Quantum-Dot Transistor (QDT) based Compute-in-Memory (CIM) architecture, without claiming silicon-level experimental verification. A comprehensive MATLAB-based simulation framework was developed to validate and analyze a previously proposed QDT-CIM architecture. The simulation implements device-level QDT models, circuit-level multiplier cells, and system-level memory arrays to perform matrix-vector multiplication operations essential for neural network inference. The validation study demonstrates strong agreement with the error rates reported in the original paper, with multiplication errors of approximately 0.1%, addition errors of 0.05%, and activation errors of 1.0%, yielding a total accumulated error of approximately 1.15%. The neural network classification experiments on synthetic MNIST-like data confirm the architectural advantages of QDT-based CIM, showing significant speedup over traditional von Neumann computing while maintaining competitive accuracy. Beyond replicating original results, this work contributes: (i) a reproducible modular simulation framework, (ii) systematic error-source decomposition identifying ADC quantization as the dominant error contributor, (iii) new analyses of device variability, IR-drop effects, and array scalability, and (iv) Quantization-Aware Training (QAT) achieving 96.8% accuracy on real MNIST data. Energy analysis estimates 0.5 pJ/MAC, while comparison with GPU implementations (~30 pJ/MAC) suggests potential improvement of up to 60×, although direct comparison requires consideration of technology node, precision, and workload differences. This work establishes a reproducible simulation framework for future research in neuromorphic computing systems.
Keywords:
compute-in-memory, quantum-dot transistor, MATLAB simulation, neural network, matrix-vector multiplication, validation study, neuromorphic computing, quantization-aware trainingReferences
M. Horowitz, "Computing’s energy problem (and what we can do about it)," in 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), Feb. 2014, pp. 10–14.
B. L. Dokic, "A Review on Energy Efficient CMOS Digital Logic," Engineering, Technology & Applied Science Research, vol. 3, no. 6, pp. 552–561, Dec. 2013.
A. Sebastian, M. Le Gallo, R. Khaddam-Aljameh, and E. Eleftheriou, "Memory devices and applications for in-memory computing," Nature Nanotechnology, vol. 15, no. 7, pp. 529–544, July 2020.
P. Deepika and N. Shylashree, "Design of an Array Multiplier for Computation in Memory Architecture," Engineering, Technology & Applied Science Research, vol. 15, no. 5, pp. 27285–27292, Oct. 2025.
D. Ielmini and H. S. P. Wong, "In-memory computing with resistive switching devices," Nature Electronics, vol. 1, no. 6, pp. 333–343, June 2018.
Y. Zhao, F. Jain, and L. Wang, "An In-Memory-Computing Structure with Quantum-Dot Transistor Toward Neural Network Applications: From Analog Circuits to Memory Arrays," International Journal of High Speed Electronics and Systems, vol. 33, no. 02n03, Sept. 2024, Art. no. 2440059.
Q. Dong et al., "A 0.3V VDDmin 4+2T SRAM for searching and in-memory computing using 55nm DDC technology," in 2017 Symposium on VLSI Circuits, June 2017, pp. C160–C161.
A. Jaiswal, I. Chakraborty, A. Agrawal, and K. Roy, "8T SRAM Cell as a Multibit Dot-Product Engine for Beyond Von Neumann Computing," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 11, pp. 2556–2567, Aug. 2019.
R. Khaddam-Aljameh, P. A. Francese, L. Benini, and E. Eleftheriou, "An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier With a Precision That Scales Linearly in Area, Time, and Power," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 2, pp. 372–385, Oct. 2021.
X. Si et al., "A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors," IEEE Journal of Solid-State Circuits, vol. 55, no. 1, pp. 189–202, Jan. 2020.
Y. Long, T. Na, and S. Mukhopadhyay, "ReRAM-Based Processing-in-Memory Architecture for Recurrent Neural Network Acceleration," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 12, pp. 2781–2794, Sept. 2018.
P. Chi et al., "PRIME: a novel processing-in-memory architecture for neural network computation in ReRAM-based main memory," SIGARCH Comput. Archit. News, vol. 44, no. 3, pp. 27–39, Mar. 2016.
M. Hu et al., "Memristor-Based Analog Computation and Neural Network Classification with a Dot Product Engine," Advanced Materials, vol. 30, no. 9, 2018, Art. no. 1705914.
S. Jain, A. Ranjan, K. Roy, and A. Raghunathan, "Computing in Memory With Spin-Transfer Torque Magnetic RAM," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 3, pp. 470–483, Mar. 2018.
J. Yang, T. Li, W. Romaszkan, P. Gupta, and S. Pamarti, "A 65-nm Digital Stochastic Compute-in-Memory CNN Processor With 8-bit Precision," IEEE Journal of Solid-State Circuits, vol. 60, no. 10, pp. 3749–3761, July 2025.
H. E. Sumbul, J. Seo, D. H. Morris, and E. Beigne, "A Fully Digital and Row-Pipelined Compute-in-Memory Neural Network Accelerator With System-on-Chip-Level Benchmarking for Augmented/Virtual Reality Applications," IEEE Micro, vol. 44, no. 2, pp. 61–70, Mar. 2024.
Y. Darma and A. Rusydi, "Quantum dot based memory devices: Current status and future prospect by simulation perspective," AIP Conference Proceedings, vol. 1586, no. 1, pp. 20–23, Feb. 2014.
J. A. Chandy and F. C. Jain, "Multiple Valued Logic Using 3-State Quantum Dot Gate FETs," in 38th International Symposium on Multiple Valued Logic (ISMVL 2008), May 2008, pp. 186–190.
Y. Lecun, L. Bottou, Y. Bengio, and P. Haffner, "Gradient-based learning applied to document recognition," Proceedings of the IEEE, vol. 86, no. 11, pp. 2278–2324, Aug. 1998.
"NVIDIA Jetson Nano Developer Kit," https://www.nvidia.com/en-us/autonomous-machines/embedded-systems/jetson-nano/product-development/.
Y. Lecun, C. Cortes, and C. J. C. Burges, "MNIST handwritten digit database." [Online]. Available: https://yann.lecun.org/exdb/mnist/index.html.
Downloads
How to Cite
License
Copyright (c) 2026 Abdulrahman Husawi

This work is licensed under a Creative Commons Attribution 4.0 International License.
Authors who publish with this journal agree to the following terms:
- Authors retain the copyright and grant the journal the right of first publication with the work simultaneously licensed under a Creative Commons Attribution License that allows others to share the work with an acknowledgement of the work's authorship and initial publication in this journal.
- Authors are able to enter into separate, additional contractual arrangements for the non-exclusive distribution of the journal's published version of the work (e.g., post it to an institutional repository or publish it in a book), with an acknowledgement of its initial publication in this journal.
- Authors are permitted and encouraged to post their work online (e.g., in institutional repositories or on their website) after its publication in ETASR with an acknowledgement of its initial publication in this journal.
