A 4-4.8GHz Adaptive Bandwidth, Adaptive Jitter Phase Locked Loop


  • H. E. Taheri Department of Electronics Engineering, Behbahan Khatam Alanbia University of Technology, Behbahan, Iran
Volume: 7 | Issue: 2 | Pages: 1473-1477 | April 2017 | https://doi.org/10.48084/etasr.1099


A low power, low phase noise adaptive bandwidth phase locked loop is presented in this paper. The proposed structure benefits from a novel lock status monitor unit (LSMU) that determines loop operation and loop bandwidth. The loop filter resistance and charge pump current are inversely proportional and bandwidth to reference frequency is maintained fixed. This structure is simulated in 0.18 μm CMOS technology and simulation results are presented.


low power, fast lock, adaptive bandwidth frequency synthesizer


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How to Cite

H. E. Taheri, “A 4-4.8GHz Adaptive Bandwidth, Adaptive Jitter Phase Locked Loop”, Eng. Technol. Appl. Sci. Res., vol. 7, no. 2, pp. 1473–1477, Apr. 2017.


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