DEEPIKA, P.; SHYLASHREE, N. Design of an Array Multiplier for Computation in Memory Architecture. Engineering, Technology & Applied Science Research, Greece, v. 15, n. 5, p. 27285–27292, 2025. DOI: 10.48084/etasr.11806. Disponível em: https://www.etasr.com/index.php/ETASR/article/view/11806. Acesso em: 24 may. 2026.