A Decision Framework for Intra Task Fixed Priority INTEL PXA270 Distributed Architecture for Soft RT- Applications Based on Deep Learning - Ayub, Nasir; Imtiaz, Muhammad Atif; Ali, Esraa; Alqahtani, Abdullah M.; Ali, Arshad; Ashurov, Mirjalol; Albouq, Sami; Law, Foong Li (Engineering, Technology & Applied Science Research, 2025)
Distributed architectures with fixed-priority scheduling using Dynamic Power Management (DPM) for CPU optimization are one of the serious concerns in INTEL PXA270. Increasing the number of transistors and task mapping on chips causes greater energy dissipation and power consumption. This study addresses the issue of system-level higher CPU energy dissipation during the execution of parallel workloads with common deadlines by introducing a framework that includes task migration based on DPM and an Adaptive Deadline First scheduling (A-DF) scheme to properly schedule migratable tasks. The DPM policy and efficient task allocation and scheduling using A-DF enhance overall throughput and optimize energy consumption to avoid delays and performance degradation in multiprocessor systems. The proposed model assigns processors to the ready task set to meet deadline requirements. A full task migration policy is also integrated to ensure proper task mapping and interprocess linkage among tasks with the same deadlines. The execution of a task can pause on one CPU and reschedule execution on another to avoid delay and ensure that the deadline is met. The proposed method shifts the context of the task from running to sleep and from idle to sleep using an adaptive DPM approach. The proposed scheme showed a promising reduction in energy dissipation compared to other conventional energy-aware task migration techniques. Simulations were conducted using a super pipelined microarchitecture Intel XScale PXA270 using instruction and data cache per core of 32 Kbyte I-cache and 32 Kbyte D-cache on various utilization factors (ui) of 18% and 20%. The proposed approach consumed 6.3% less energy and achieved 2.1% and 2.4% improvements in terms of accuracy and precision when almost half of the CPU is running, and on a lower workload consumed 1.04% less energy. The proposed design provided significant improvements in clock rates of 100, 104, and 116 MHz.