A Novel Architecture Design of a USB Module in Wireless Modem for IOT Applications


  • Annavarapu Praneeth Department of ECE, KLEF, Vaddeswaram, Guntur, Andhra Pradesh, India
  • Govardhani Immadi Department of ECE, KLEF, Vaddeswaram, Guntur, Andhra Pradesh, India
  • V. S. V. Prabhakar Department of CSE, GITAM School of Technology, GITAM deemed to be University, Visakhapatnam, India
  • Venkata Narayana Madhava Reddy Department of ECE, KLEF, Vaddeswaram, Guntur, Andhra Pradesh, India
Volume: 14 | Issue: 3 | Pages: 14200-14205 | June 2024 | https://doi.org/10.48084/etasr.7163


Embedded micro-electro-mechanical technologies and network connectivity allow for the integration of sensing, identification, and communication capabilities into a variety of smart devices. These intelligent devices can automatically link to create the Internet of Things (IoT). The greater power consumption of a scan-based test has been one of the biggest problems since Very Large-Scale Integration (VLSI) architecture was introduced. There are too many switches made during the scan shifting procedures due to the enormous number of the scan cells. The design and implementation of an IoT access point are presented in this paper using the Logic Vision tool. In the semiconductor sector, scan chains are frequently employed for structural testing following fabrication or production. In this paper, a new architecture was designed with USB protocol, which reduces dynamic power, and fault-free circuits were constructed. The proposed architecture can work with the current one without changing the decompression architecture. Experimental findings on commercial circuits demonstrate that this strategy minimizes the scan shifting power.


USB, JTAG, scan chains, logic vision, Design-for-Testability (DFT), Logic Built-In Self-Test (LBIST)


Download data is not yet available.


"CS301: Logic Gates," Saylor Academy. https://learn.saylor.org/mod/


E. Alpaslan, Y. Huang, X. Lin, W.-T. Cheng, and J. Dworak, "On Reducing Scan Shift Activity at RTL," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 7, pp. 1110–1120, Jul. 2010.

P. Girard, "Survey of low-power testing of VLSI circuits," IEEE Design & Test of Computers, vol. 19, no. 3, pp. 82–92, Jun. 2002.

W.-L. Li, P.-H. Wu, and J.-C. Rau, "Reducing switching activity by test slice difference technique for test volume compression," in IEEE International Symposium on Circuits and Systems, Taipei, Taiwan, Dec. 2009, pp. 2986–2989.

A. Chandra and K. Chakrabarty, "Combining low-power scan testing and test data compression for system-on-a-chip," in 38th annual Design Automation Conference, Las Vegas, NV, USA, Jun. 2001, pp. 166–169.

X. Lin and Y. Huang, "Scan Shift Power Reduction by Freezing Power Sensitive Scan Cells," Journal of Electronic Testing, vol. 24, no. 4, pp. 327–334, Aug. 2008.

C. P. Ravikumar, M. Hirech, and X. Wen, "Test strategies for low power devices," in Conference on Design, automation and test in Europe, Munich, Germany, Mar. 2008, pp. 728–733.

IEEE Standard Test Access Port and Boundary-Scan Architecture. IEEE, 1990.

B. L. Dokic, "A Review on Energy Efficient CMOS Digital Logic," Engineering, Technology & Applied Science Research, vol. 3, no. 6, pp. 552–561, Dec. 2013.

TetraMAX ATPG User Guide, version I-2013.12-SP4. Synopsys Inc., 2013

TetraMAX ATPG User Guide, Version C-2009.06-SP2. Synopsys Inc., 2009.

Cadence Encounter Timing System User Manual. Cadence, 2012.

IEEE 1149.1 Working Group, "JTAG IEEE 1149.1 Standard WG," IEEE. https://grouper.ieee.org/groups/1149/1/.

J. Lee, M. Tebranipoor, and J. Plusquellic, "A low-cost solution for protecting IPs against scan-based side-channel attacks," in 24th IEEE VLSI Test Symposium, Berkeley, CA, USA, April 2006, pp. 94–99.

H. Fujiwara and M. E. J. Obien, "Secure and testable scan design using extended de Bruijn graphs," in 15th Asia and South Pacific Design Automation Conference, Taipei, Taiwan, Jan. 2010, pp. 413–418.

D. Hely, F. Bancel, M.-L. Flottes, and B. Rouzeyre, "A secure Scan Design Methodology," in Design Automation & Test in Europe Conference, Munich, Germany, Mar. 2006, vol. 1, pp. 1–2.

M. A. Razzaq, V. Singh, and A. Singh, "SSTKR: Secure and Testable Scan Design through Test Key Randomization," in Asian Test Symposium, New Delhi, India, Nov. 2011, pp. 60–65.

R. A. Shafik, J. Mathew, and D. K. Pradhan, "A Low-Cost Unified Design Methodology for Secure Test and Intellectual Property Core Protection," IEEE Transactions on Reliability, vol. 64, no. 4, pp. 1243–1253, Dec. 2015.

U. Chandran and D. Zhao, "SS-KTC: A High-Testability Low-Overhead Scan Architecture with Multi-level Security Integration," in 27th IEEE VLSI Test Symposium, Santa Cruz, CA, USA, May 2009, pp. 321–326.

R. Sankaralingam, R. R. Oruganti, and N. A. Touba, "Static compaction techniques to control scan vector power dissipation," in 18th IEEE VLSI Test Symposium, Montreal, QC, Canada, May 2000, pp. 35–40.

S. Paul, R. S. Chakraborty, and S. Bhunia, "VIm-Scan: A Low Overhead Scan Design Approach for Protection of Secret Key in Scan-Based Secure Chips," in 25th IEEE VLSI Test Symposium, Berkeley, CA, USA, May 2007, pp. 455–460.

J. Da Rolt, G. Di Natale, M.-L. Flottes, and B. Rouzeyre, "A smart test controller for scan chains in secure circuits," in 19th International On-Line Testing Symposium, Chania, Greece, Jul. 2013, pp. 228–229.

Maestra Comprehensive Test for Satellite Testing V5. Maestra, 2012.


How to Cite

A. Praneeth, G. Immadi, V. S. V. Prabhakar, and V. N. M. Reddy, “A Novel Architecture Design of a USB Module in Wireless Modem for IOT Applications”, Eng. Technol. Appl. Sci. Res., vol. 14, no. 3, pp. 14200–14205, Jun. 2024.


Abstract Views: 116
PDF Downloads: 42

Metrics Information

Most read articles by the same author(s)